PIC18LF66K80-I/PT【PDF 40/351 页】MCU PIC ECAN 64KB FLASH 64TQFP

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PIC18F66K80 FAMILY

DS39977F-page 134

2010-2012 Microchip Technology Inc.

7.4

Erasing Flash Program Memory

The erase blocks are 32 words or 64 bytes.

Word erase in the Flash array is not supported.

When initiating an erase sequence from the micro-

controller itself, a block of 64 bytes of program memory

is erased. The Most Significant 16 bits of the

TBLPTR<21:6> point to the block being erased. The

TBLPTR<5:0> bits are ignored.

The EECON1 register commands the erase operation.

The EEPGD bit must be set to point to the Flash

program memory. The WREN bit must be set to enable

write operations. The FREE bit is set to select an erase

operation.

For protection, the write initiate sequence for EECON2

must be used.

A long write is necessary for erasing the internal Flash.

Instruction execution is halted while in a long write

cycle. The long write will be terminated by the internal

programming timer.

7.4.1

FLASH PROGRAM MEMORY

ERASE SEQUENCE

The sequence of events for erasing a block of internal

program memory location is:

Load the Table Pointer register with the address

of row to be erased.

Set the EECON1 register for the erase operation:

Set the EEPGD bit to point to program memory

Clear the CFGS bit to access program memory

Set the WREN bit to enable writes

Set the FREE bit to enable the erase

Disable the interrupts.

Write 55h to EECON2.

Write 0AAh to EECON2.

Set the WR bit.

This begins the row erase cycle.

The CPU will stall for the duration of the erase

for TIW. (See Parameter D133A.)

Re-enable interrupts.

EXAMPLE 7-2:

ERASING A FLASH PROGRAM MEMORY ROW

MOVLW

CODE_ADDR_UPPER

; load TBLPTR with the base

MOVWF

TBLPTRU

; address of the memory block

MOVLW

CODE_ADDR_HIGH

MOVWF

TBLPTRH

MOVLW

CODE_ADDR_LOW

MOVWF

TBLPTRL

ERASE_ROW

BSF

EECON1, EEPGD

; point to Flash program memory

BCF

EECON1, CFGS

; access Flash program memory

BSF

EECON1, WREN

; enable write to memory

BSF

EECON1, FREE

; enable Row Erase operation

BCF

INTCON, GIE

; disable interrupts

Required

MOVLW

55h

Sequence

MOVWF

EECON2

; write 55h

MOVLW

0AAh

MOVWF

EECON2

; write 0AAh

BSF

EECON1, WR

; start erase (CPU stall)

BSF

INTCON, GIE

; re-enable interrupts

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